1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, this invention relates to contact electrodes and a wiring structure, which constitute a semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1 is a cross section illustrating the structure of a contact electrode and metal wiring which are used in a conventional semiconductor device. A method of manufacturing the contact electrode and the metal wiring in the conventional semiconductor integrated circuit will be described. An impurity is implanted into a semiconductor substrate 1 to form a diffusion region 2, then a first interlayer insulating film 3 is formed. Then, the insulating film 3 on the diffusion region 2 is etched by an RIE (Reactive Ion Etching) technique so as to make a contact hole through which the surface of the diffusion region 2 is partially exposed. Further, a metal layer is formed on the insulating film 3 so as to cover the contact hole 4, and first wiring layers 5 and 6 are formed using the photolithography technique and the RIE technique. A second insulating film 7 is formed on the insulating film 3 to cover the wiring layers 5 and 6. A VIA hole 8 is formed in the insulating film 7 on the wiring layer 6 so as to partially expose the surface of the wiring layer 6. Then, a second wiring layer 9 is patterned on the insulating layer 7 so as to cover the VIA hole 8.
According to the above-described manufacturing method, there are mask alignment tolerances as shown by reference numerals, 10, 11, 12, and 13 in FIG. 1: a numeral "10" is a clearance between the diffusion region 2 and the contact hole 4, "11" between the wiring layer 5 and the contact hole 4, "12" between the wiring layer 6 and the VIA hole 8, and "13" between the wiring layer 9 and the VIA hole. If a misalignment occurs even slightly without such clearances, at the time of forming the contact hole 4, for example, the difference in the etching rate will cause the following shortcomings:
That part of the substrate 1 which is not connected to the diffusion layer 2 may be deeply etched; in forming the VIA hole 8, etching may be done on not only that part of the insulating film 3 which is off the wiring layers 6, but also on the substrate 1 through the film 3- This may cause various problems, such as electric shorting between the second wiring layer 9 and the substrate 1 at the time of processing the wiring layer 9.
For prevention of defects caused by the possible variation in mask alignment and in process, the alignment tolerances 10, 11, 12 and 13 between the wiring layers are set to as large as 0.5 to 1.0 .mu.m. These mask alignment tolerances, however, considerably hinder finer patterning of the wiring and the contact size.